Title Memory Address Decoder for TAPR TUC-52 Pattern TUC52 Revision B ; Revision History: ; ; B 13 Dec. 1994 Updated design and convert to 16V8. -rah ; A 23 Nov. 1993 Initial prototype design using 16L8. -rah Author R. A. Hansen, bhansen@stny.lrun.com Company Tucson Amateur Packet Radio Date 13 Dec. 1994 CHIP MEM_DECODER PAL16V8 ; The PALASM software won't accept 18CV8, so we use 16V8 which has ; (mostly) the same architecture. ;---------------------------------- PIN Declarations --------------- PIN 1 /ShuntA ; I0/CLK PIN 2 /ShuntB ; I1 PIN 3 /ShuntC ; I2 PIN 4 /ShuntD ; I3 PIN 5 A10 ; I4 PIN 6 A11 ; I5 PIN 7 A12 ; I6 PIN 8 A13 ; I7 PIN 9 A14 ; I8 PIN 10 GND ; GND PIN 11 A15 ; I9/OE* PIN 12 /IOA combinatorial ; F0 output - I/O Select A PIN 13 /IOB combinatorial ; F1 output - I/O Select B PIN 14 /PSEN combinatorial ; F2 input - PIN 15 /RD combinatorial ; F3 input - PIN 16 /WR combinatorial ; F4 input - PIN 17 /XCE combinatorial ; F5 output - chip enable X PIN 18 /YCE combinatorial ; F6 output - chip enable Y PIN 19 /ZCE combinatorial ; F7 output - chip enable Z PIN 20 VCC ; n/a ;-------------------- Equation Segment -------------------- EQUATIONS ; I/O Select A IOA.TRST = VCC IOA = /PSEN * A15 * A14 * A13 * A12 * A11 * /A10 ; F8XX-FBXX ; I/O Select B FCXX-FFXX IOB.TRST = VCC IOB = /PSEN * A15 * A14 * A13 * A12 * A11 * A10 * ShuntC + /PSEN * A15 * A14 * A13 * A12 * A11 * A10 * /ShuntC * RD + /PSEN * A15 * A14 * A13 * A12 * A11 * A10 * /ShuntC * WR ; Chip Enable Z (code and data) 8000-EFFF ZCE.TRST = VCC ZCE = A15 * /A14 ; 8XXX-BXXX + A15 * /A13 ; 8XXX-9XXX, CXXX-DXXX + A15 * /A12 ; 8XXX, AXXX, CXXX, EXXX ; Chip Enable Y (RAM) YCE.TRST = VCC YCE = /ShuntB * /ShuntA * /A15 ; 0000-7FFF +/ShuntB * ShuntA * /A15 * /A14 * A13 ; 2000-3FFF | +/ShuntB * ShuntA * /A15 * A14 ; 4000-7FFF | + ShuntB * /ShuntA * /A15 * A14 ; 4000-7FFF + ShuntB * ShuntA * /A15 ; 0000-7FFF ; Chip Enable X (ROM) XCE.TRST = VCC XCE = /ShuntB * /ShuntA * /A15 ; 0000-7FFF +/ShuntB * ShuntA * /A15 * /A14 * /A13 ; 0000-1FFF + ShuntB * /ShuntA * /A15 * /A14 ; 0000-3FFF + ShuntB * ShuntA ; 0000-FFFF ; Setup Function Pins to act as inputs. ; We have to disable output tri-state buffer, but we can't use ; an expression like: PIN.TRST = GND because then the input ; will come from the adjacent I/O pin, instead of the desired ; I/O pin. To overcome this we set up the pin as I/O but use ; a tri-state term that is never true. PSEN.TRST = ShuntA * /ShuntA ; never true, buffer always off RD.TRST = ShuntA * /ShuntA WR.TRST = ShuntA * /ShuntA PSEN = GND ; more kluges to force PALASM to use the proper pin polarity RD = GND WR = GND ;-------------------- Simulation -------------------- SIMULATION ; Test memory select outputs, option 1 (no shunts) setf /shunta /shuntb /shuntc /shuntd ; addr=0000 setf /a15 /a14 /a13 /a12 /a11 /a10 /psen /rd /wr check xce yce /zce /ioa /iob setf psen rd wr ; independent of control lines check xce yce /zce /ioa /iob ; addr=8000 setf a15 check /xce /yce zce /ioa /iob setf /psen /rd /wr ; independent of control lines check /xce /yce zce /ioa /iob ; Test memory select outputs, option 2 (shunt A only) setf shuntA ; addr=0000 setf /a15 /a14 /a13 /a12 /a11 /a10 /psen /rd /wr check xce /yce /zce /ioa /iob setf psen rd wr ; independent of control lines check xce /yce /zce /ioa /iob ; addr=2000 setf a13 check /xce yce /zce /ioa /iob setf /psen /rd /wr ; independent of control lines check /xce yce /zce /ioa /iob ; addr=8000 setf a15 /a13 check /xce /yce zce /ioa /iob setf psen rd wr ; independent of control lines check /xce /yce zce /ioa /iob ; Test memory select outputs, option 3 (shunt B only) setf /shuntA shuntB /shuntc /shuntd ; addr=0000 setf /a15 /a14 /a13 /a12 /a11 /a10 /psen /rd /wr check xce /yce /zce /ioa /iob setf psen rd wr ; independent of control lines check xce /yce /zce /ioa /iob ; addr=4000 setf a14 check /xce yce /zce /ioa /iob setf /psen /rd /wr ; independent of control lines check /xce yce /zce /ioa /iob ; addr=8000 setf a15 /a14 check /xce /yce zce /ioa /iob setf psen rd wr ; independent of control lines check /xce /yce zce /ioa /iob ; Test memory select outputs, option 4 (shunts A and B) setf shuntA shuntB ; addr=0000 setf /a15 /a14 /a13 /a12 /a11 /a10 /psen /rd /wr check xce yce /zce /ioa /iob setf psen rd wr ; independent of control lines check xce yce /zce /ioa /iob ; addr=8000 setf a15 check xce /yce zce /ioa /iob setf /psen /rd /wr ; independent of control lines check xce /yce zce /ioa /iob ; Test I/O outputs; option 1 (shunt c) setf shuntC ; addr=F800 setf a15 a14 a13 a12 a11 /a10 /psen /rd /wr check ioa /iob setf rd wr ; independent of rd/wr check ioa /iob setf psen ; not active during psen check /ioa /iob ; addr=FC00 setf a15 a14 a13 a12 a11 a10 /psen /rd /wr check /ioa iob setf rd wr ; independent of rd/wr check /ioa iob setf psen ; not active during psen check /ioa /iob ; Test I/O outputs; option 2 (no shunt c) setf /shuntC ; addr=F800 setf a15 a14 a13 a12 a11 /a10 /psen /rd /wr check ioa /iob setf rd wr ; independent of rd/wr check ioa /iob setf psen ; not active during psen check /ioa /iob ; addr=FC00 setf a15 a14 a13 a12 a11 a10 /psen /rd /wr check /ioa /iob setf rd /wr ; just RD check /ioa iob setf wr /rd ; just WR check /ioa iob setf rd wr ; both RD and WR check /ioa iob setf psen ; not active during psen check /ioa /iob ; A 18CV8 PAL is used at IC8 to generate chip selects for the ; different devices used on TUC52. The actual memory mapping is ; determined by the programming of the PAL. The user selects a ; particular pre-programmed memory map by placing shunts on P13. ; ; In general, XCE* (active low) selects the EPROM at IC4, YCE* ; (active low) selects the RAM at IC5 and ZCE* (active low) selects ; the RAM/ROM at IC6. ; ; IOA* is an I/O select line (active low) that's determined by ; address leads from the processor. It drives one half of IC9 for ; I/O device selection. IOB* is an I/O select line (active low) ; whose state is also determined by the address signals. ; Additionally, IOB* can also be configured to qualify its signal ; with RD* or WR* being active (low). This qualication may be needed ; for dumb ports (like 74hc374). The IOA* and IOB* signals are ; always inactive (high) when PSEN* is active (low). ; ; The PAL outputs should be programmed as described below. For shunt ; inputs A, B, C and D, an "open" results in a logic high at that ; input while a "shunt" results in a logic low at that input. ; ; TABLE 1 -- ADDRESS SELECTION ; ; Shunts A and B determine main memory mapping. ; ; SHUNTS ADDRESS-WHEN-SIGNAL-IS-ACTIVE ; B A IC4 (XCE*) IC5 (YCE*) IC6 (ZCE*) ; ==== ==== ========== ========== ========== ; open open 0000-7FFF 0000-7FFF 8000-EFFF ; open shnt 0000-1FFF 2000-7FFF 8000-EFFF ; shnt open 0000-3FFF 4000-7FFF 8000-EFFF ; shnt shnt 0000-FFFF 0000-7FFF 8000-EFFF ; ; Shunt C determines I/O space mapping. ; ; SHUNT BUS-CNTL-SIGS ADDRESS-WHEN-ACTIVE ; C PSEN* RD* WR* IOA* IOB* ; ==== ===== === === ========= ========= ; shnt 1 x x F800-FBFF FC00-FFFF ; open 1 0 0 F800-FBFF FC00-FFFF ***** ; open 1 0 1 F800-FBFF FC00-FFFF ; open 1 1 0 F800-FBFF FC00-FFFF ; open 1 1 1 F800-FBFF no select ; ; **** RD* and WR* should never be low at same time -- this ; state is shown for completeness of PAL programming. ; ; Shunt D currently has no effect on the PAL. ;